The present invention relates generally to semiconductor processing technology, and more particularly to a method for planarizing semiconductor structures.
A chemical mechanical polishing (CMP) process is a semiconductor processing technology that is used for planarizing a surface of a semiconductor structure. Various types of high selectivity slurry (HSS) are often applied during the CMP process for providing a higher polish rate for one material than another. For example, the HSS is often used in the CMP process during the formation of shallow trench isolation (STI) structures. Conventionally, the STI structures are constructed by performing a series of process steps. A silicon nitride layer having a plurality of openings is deposited on a semiconductor substrate. An etching step is performed, using the silicon nitride layer as a mask, to form a plurality of trenches through the openings in the semiconductor substrate. A silicon oxide layer is deposited in the trenches and on the silicon nitride layer. The CMP process is then performed, using HSS for providing the silicon oxide layer with a higher polish rate than that of the silicon nitride layer.
Conventionally, the CMP using HSS is performed in a continuous process without interruption. While the continuous process of applying HSS can remove most of the silicon oxide layer, the polish rate of HSS will slow down over time, especially in an area of the semiconductor substrate where the pattern density of the trenches is high. This may cause an undesired step height variation across the high pattern density area and the low pattern density area. Thus, divots may be formed on the semiconductor substrate.
It is desirable to have a planarization method for providing a semiconductor structure with a reduced step height variation across the high pattern density area and the low pattern density area.